1. Field of the Invention
The invention relates to a memory device, and in particular, to a memory device with a length-controllable channel and a fabrication method thereof.
2. Description of the Related Art
A dynamic random access memory (DRAM) utilizes charging alternation of capacitors disposed in memory cells to store information. With continued DRAM miniaturization and fabrication thereof, a reduced substrate area of a memory cell is required to increase the density of memory cells in integrated circuits. However, having a sufficiently large surface area of an electrode plate of memory cells to store charges is still essential. Currently, for example, a trench capacitor with a trench-type capacitor storage area formed in the substrate can effectively reduce the occupied area of memory cells.
Specifically, a conventional vertical transistor associated with an underneath trench capacitor can provide a proper gate length and a low leakage current, so that a high bit line voltage and a small lateral area are achieved.
A conventional memory device structure is shown in FIG. 1. A memory device 1 comprises a substrate 2, a trench 3, a trench capacitor 4, a top dielectric layer 5, a gate oxide layer 6, a gate 7, a source S and a drain D.
The trench 3 is formed in the substrate 2. The trench capacitor 4 is formed in the lower portion of the trench 3. The top dielectric layer 5 is formed in the trench 3, leaving a long distance from the top dielectric layer 5 to the surface of the substrate 2. The gate 7 is formed on the top dielectric layer 5. The gate oxide layer 6 is formed between the gate 7 and the substrate 2. The source S and the drain D are formed on both sides of the trench 3 in the substrate 2.